universal ic programmer kit|flash ic programmer|Automated Device Programmers-System General

Acroview, a leader in chip programming, has announced further expansion of its compatible chip model coverage with the release of a new version of its programming software. The company's core product, the universal programming platform AP8000, has now been fully adapted to support SinOne's motor drive microcontroller SC32M155C6P.

The SC32M155C6P is an industrial-grade, 32-bit Flash microcontroller based on the Arm Cortex®-M0+ core, designed specifically for motor drive applications, with an operating frequency of up to 72MHz. The Cortex®-M0+ core uses a 32-bit reduced instruction set (RISC) and complies with the CMSIS standard.

The SC32M155C6P features powerful data processing capabilities. The integrated Direct Memory Access (DMA) controller enables high-speed data transfer, while the hardware CRC module and the integrated MathRhythm (MR) unit further accelerate data computation.

The SC32M155C6P microcontroller embeds a high-precision high-frequency internal oscillator (HIRC) and a low-frequency 32kHz internal oscillator (LIRC), and also provides an interface for an external 32.768kHz low-frequency crystal oscillator (LXT). Both the embedded clock sources and the external crystal interface can provide clock signals for the system. The built-in system clock monitoring module has a clock source switching function: when the system clock becomes abnormal, it can automatically switch the clock source to the HIRC to ensure stable system operation.

The SC32M155C6P microcontroller is rich in peripherals, including: up to 44 GPIOs with external interrupt capability, four 16-bit timers, eight channels of 16-bit enhanced multi-function EPWM (with complementary dead-time and fault detection), three independent UARTs (UART2 has a full LIN interface supporting master/slave mode), an independent CAN interface (supporting CAN specification 2.0B and CAN FD), two SPIs, two TWIs, an independent PCAP module, two independent QEP modules, three analog comparators CMP0~2, and an additional independent analog comparator CMP3. Furthermore, it features three independent operational amplifiers, a 10-bit DAC, 18 channels of 12-bit high-precision high-speed ADC (supporting dual-channel simultaneous sample-and-hold and threshold alarm), a temperature sensor module, an independent watchdog timer (WDT), and a low-voltage reset circuit (LVR), effectively enhancing system reliability.

The SC32M155C6P microcontroller supports a wide operating voltage range of 2.0-5.5V and can operate at ambient temperatures from -40°C to 105°C. Additionally, this series offers three power modes to meet the power consumption requirements of different application scenarios, achieving a balance between high performance and low power.

The SC32M155C6P microcontroller uses industry-leading eFlash process technology, with Flash write endurance of over 100,000 cycles and data retention of 100 years at room temperature. It exhibits excellent ESD performance and EFT immunity. The SC32M155C6P provides up to 128 Kbytes of APROM space, 8 Kbytes of SRAM (with parity check support), 2 Kbytes of user storage area (EEPROM-like), and 4 Kbytes of system memory area (LDROM). The built-in system memory area supports OTA upgrades, and multiple program upgrade methods such as ISP (In System Programming), ICP (In Circuit Programming), and IAP (In Application Programming) are available, allowing on-board debugging and program upgrades online or under power.

The SC32M155C6P offers excellent characteristics combined with outstanding anti-interference performance, making it suitable for various motor drive solutions and main control solutions. Application areas include: motor drives, smart home appliances, smart home, IoT, new energy, and other industrial control and consumer fields.

Main Features

Operating Conditions

• Operating Voltage: 2.0V ~ 5.5V

• Operating Temperature: -40°C ~ +105°C

EMS

• ESD
  -- HBM: JS-001-2023 Class 3A
  -- MM: JEDEC EIA/JESD22-A115 Class C
  -- CDM: ANSI/ESDA/JEDEC JS-002-2022 Class C3

• EFT
  -- EN61000-4-4 Level 4

Package Types

• 28 PIN: TSSOP28

• 32 PIN: LQFP32(7X7)/QFN32(4X4)

• 48 PIN: LQFP48(7X7)/QFN48(5X5)

Core

• Cortex®-M0+ core

• WIC (wakeup interrupt controller) module

• 64-bit instruction prefetch

• Built-in multiplier

Reset

• Power-on reset (POR)

• Software RST reset

• External NRST pin (PC11) low-level reset

• Watchdog timer (WDT) reset

• Low-voltage reset (LVR)
  -- Four selectable reset voltage levels: 4.3V, 3.7V, 2.9V, 1.9V
  -- Default value is the option selected by the user's Code Option

Bus

• 1 IOPORT

• 1 AHB

• 3 APBs: APB0~APB2

Power-Saving Modes

• Slow mode: System clock source can be LIRC, CPU can run at 32kHz

• IDLE Mode, wake-up by any interrupt

• STOP Mode, wake-up by INT0~15, Base Timer, and CMP

Memory

Main APROM

• Up to 128 Kbytes APROM

• 100,000 write cycles

• Hardware read protection encryption

• Hardware write protection: Two IAP-prohibited areas configurable via Code Option, minimum setting unit of 512 bytes (one sector)

System Memory LDROM

• 4 Kbytes system memory area, factory-programmed with BootLoader

SRAM

• 8 Kbytes Internal SRAM

• Parity check support
  -- Additional 1K RAM for parity: SRAM data bus width is 36 bits, of which 4 bits are used for parity (1 bit per byte)
  -- Parity bits are calculated and stored when writing to SRAM, and automatically checked when reading. If a bit fails, an NMI is generated.
  -- Independent SRAM parity error flag SRAMPEIF
  -- Note: SRAM needs initialization when used.

• Boot from SRAM supported

2 Kbytes User Storage Area (EEPROM-like)

• Divided into 4 sectors of 512 bytes each

• 100,000 write cycles

• Data retention 100 years at 25°C

96-bit Unique ID

• 96-bit unique ID provided in IFB area

BootLoader

• Hardware method: System memory area: 4 Kbytes, factory-programmed BootLoader

• Software method: Supports interrupt vector table remapping, allowing flexible allocation of user BootLoader area from APROM

Programming and Debugging

• Supports ICP/ISP/IAP programming methods

• 2-wire JTAG/SWD programming and debug interface

• Simulation not supported in encrypted state

Clock Sources

Built-in 72MHz High-Frequency Internal Oscillator (HIRC)

• As system clock source

• Default system clock frequency on power-up: fSYS = fHIRC/2

• Frequency tolerance: ≤±1% across (2.0V~5.5V) and (-40°C~105°C) application environment

• Automatic calibration via external 32.768kHz crystal, after which HIRC accuracy can approach that of the external 32.768kHz crystal

Built-in 32kHz Low-Frequency Internal Oscillator (LIRC)

• As system clock source

• Fixed as WDT clock source; when WDT is enabled, this clock source must be turned on

• As Base Timer clock source, can wake up from STOP

• Frequency tolerance: ≤±4% after register trimming across (4.0~5.5V) and 25°C application environment

External 32.768kHz Low-Frequency Crystal Oscillator (LXT)

• As system clock source

• As Base Timer clock source

• External 32.768kHz oscillator

• Can be used to automatically calibrate HIRC

Interrupt Sources

• 27 interrupt sources

• Four programmable interrupt priority levels

• External interrupts INT
  -- 16 INT interrupt sources, sharing 4 interrupt vectors
  -- INT can be switched to cover all GPIO pins
  -- All configurable for rising edge, falling edge, or both edges, each with independent interrupt flags
  -- Software can set corresponding interrupt flags to trigger interrupts

Digital Peripherals

Up to 44 Bidirectional Independently Controllable GPIOs

• Independent pull-up resistor setting

• All IOs have high sink current drive capability (50mA)

Watchdog Timer (WDT)

• Built-in WDT, overflow time programmable from 3.94ms to 500ms

Base Timer (BTM)

• Selectable clock source: LXT or LIRC

• Interrupt frequency interval selectable from 15.625ms to 32s

• Can wake up from STOP Mode

Four 16-bit Timer/Counters (TIM) Timer0~Timer3

• 16-bit up, down, up/down auto-reload counter

• Supports rising/falling edge capture,可实现 PWM duty cycle and period capture

• Each TIM provides two PWM outputs (TPWMA/TPWMB) with same period and adjustable duty cycle

• Timer overflow and capture events of TIM1 and TIM2 can trigger DMA requests

• All Timer Tn/TnCAP/TnPWMA and TnEX/TnPWMB pins support remapping

Eight-Channel 16-bit Advanced Multi-Function EPWM

• Enhanced 8-channel 16-bit common-period multi-function EPWM
  -- Each EPWM output can be individually enabled
  -- Each EPWM has an individually adjustable compare value, so duty cycle can be set independently
  -- Output waveform of each EPWM can be individually inverted

• EPWM output order programmable

• Link function: Provides four EPWM compare values; when EPWM counter reaches the set compare value, it can trigger corresponding ADC sequence sampling

• Alignment modes
  -- Center-aligned, including symmetric and asymmetric center-aligned modes
  -- Edge-aligned

• Independent mode or complementary mode
  -- In independent mode, all 8 EPWM channels share the same period, but the turn-on point and output waveform toggle compare value for each channel can be adjusted individually
  -- In complementary mode, four groups of complementary EPWM waveforms with dead-time can be output simultaneously

• Fault detection mechanism
  -- Six fault trigger sources: software trigger, CMP0, CMP3, OP1, OP2, and external FLT pin
  -- Two fault response modes: cycle-by-cycle and one-shot
  -- Each trigger source can independently set trigger level and fault response mode
  -- Upon fault trigger, the output state of each EPWM channel is individually configurable
  -- Fault detection input signal filtering time programmable

• Two overflow interrupts: up-overflow and down-overflow interrupts

• Two fault response interrupts: cycle-by-cycle and one-shot

Three-Phase Capture Module (PCAP)

• Includes an independent 24-bit auto-reload counter with programmable count threshold

• Three PCAP input signals: PCAP0/PCAP1/PCAP2

• Two-stage input signal filtering, pre- and post-filter capture level status readable

• Counter overflow and edge capture events can trigger DMA requests

• Phase discrimination: can detect timing anomalies for three-phase signals with 60°/120° phase difference

Two Independent Quadrature Encoder Pulse (QEP) Modules

• Can interface with linear or rotary incremental encoders to obtain machine position, direction, etc.

• Three counting modes
  -- Quadrature counting
  -- Direction counting
  -- Dual pulse counting

• Each QEP module provides three input signals: QEPnA, QEPnB, and QEPnI, n=0~1
  -- QEPnA and QEPnB input direction can be swapped
  -- Input polarity of QEPnA and QEPnB individually configurable
  -- Digital input filter with up to 128 division for QEPnA, QEPnB, and QEPnI signals

• In direction counting and dual pulse counting modes,可以选择 rising edge, falling edge, or both edges

• Position counter provides two reset modes: index event reset, overflow reset

• Four interrupt sources
  -- Overflow interrupt
  -- Underflow interrupt
  -- Index reset interrupt
  -- Edge-triggered interrupt

Three Independent UART Communication Ports UART0~2

• UART2 is a full LIN interface
  -- Master/slave mode switchable
  -- Supports hardware break sending in master mode (10/13 bits)
  -- Supports hardware break detection in slave mode (10/11 bits)
  -- Supports baud rate synchronization in slave mode
  -- Provides related interrupts/status bits/flag bits

• Each UART signal pair can be switched to two groups of IOs
  -- UART0 mapped to programming pins supports only half-duplex communication

• Independent baud rate generator

• UART0/1 support wake-up from STOP mode

• Three communication modes selectable
  -- Mode 0: 8-bit half-duplex synchronous communication
  -- Mode 1: 10-bit full-duplex asynchronous communication
  -- Mode 3: 11-bit full-duplex asynchronous communication

• UART0 and UART1 support DMA requests

• UART2 does not support DMA

One Independent SPI Communication Port SPI0

• SPI0 signals can be switched to two groups of IOs

• Provides 16-bit 8-level FIFO, separate for transmit and receive

• Signal drive strength enhanced in SPI mode

• Supports DMA

One Independent TWI Communication Port TWI0

• TWI0 signals can be switched to three groups of IOs

• Configurable as master or slave mode

• Supports clock stretching in slave mode

• Communication rate up to 1Mbps

• TWI0 supports DMA

One Combined Communication Port SPI1 & TWI1

• SPI1 and TWI1 functions are completely independent, with shared registers and signal pins

• SPI1 and TWI1 signals can be switched to four groups of IOs

• SPI1 supports DMA

• TWI1
  -- Configurable as master or slave mode
  -- Supports clock stretching in slave mode
  -- Communication rate up to 1Mbps

CAN Communication Port

• Protocol support
  -- CAN specification 2.0B
  -- CAN FD

• Standby mode support

• Timestamp
  -- CiA 603: 64-bit timestamp, one timestamp for transmitted frames (TTS) stored in register, but each received frame (RTS) has an individual timestamp

• Transmit/Receive buffers
  -- 8 Receive Buffers (RB)
  -- 9 Transmit Buffers (TB)
  -- 8 Receive Filters (supporting 29 bits)

Built-in CRC Check Module

• Initial value programmable, default 0xFFFF_FFFF

• Polynomial programmable, default 0x04C1_1DB7

• Supports 8/16/32-bit data units

DMA

• 4 independently configurable channels

• Each DMA channel can send DMA requests to other channels

• Data width supports byte, half-word, word

• 23 DMA request sources, four request priority levels

• Supports source/destination address auto-increment or fixed

• Supports single and burst transfer modes

• Transfer types: memory-to-memory, memory-to-peripheral, peripheral-to-memory, peripheral-to-peripheral

Analog Peripherals

Reference Voltage Options for Analog Peripherals (5 choices)

• VDD, 2.4V, 2.048V, 1.024V, and external Vref pin input

Built-in Voltage Reference Module VREF

• Built-in three reference voltages: 2.4V, 2.048V, 1.024V

• External Vref input can be selected as system analog circuit reference

• VDD can be selected as system analog circuit reference

• ADC/DAC/OP can independently choose reference source from VDD or VREF module

Digital-to-Analog Converter (DAC)

• Resolution: 10-bit

• Output methods
  -- Two independent DAC output ports DACOUT0 and DACOUT1
  -- Internally can output to inverting input of OP1/OP2
  -- Can output to negative input of CMP0/1/2/3

Analog-to-Digital Converter (ADC)

• Resolution: 12-bit

• Supports up to 18 channels
  -- 16 external ADC sampling channels AIN0 ~ AIN15
  -- Three AIN pins shared with OP, can measure OP module output signals: OP0, OP1, OP2
  -- One internal channel directly measures VDD voltage
  -- One internal temperature sampling channel

• ADC threshold watchdog, can set both upper and lower thresholds, can trigger interrupt

• Two sample-and-hold circuits
  -- Support simultaneous sampling of two channels
  -- Single sampling mode or dual sampling mode selectable

• Trigger modes selectable
  -- Manual trigger (software trigger)
  -- Sequence trigger: Four sequences programmable, can trigger sequence sampling via EPWM counter value

• ADC conversion complete interrupt, each of the four sequences has independent conversion complete interrupt and flag

• Single conversion time approx. 404ns

• Supports DMA transfer: ADC conversion complete can generate DMA request

• ADC conversion result supports overflow notification; when overflow occurs, OVERRUN flag is set, and the OVERRUN flag and ADC conversion result are in the same register ADCV for one-time read

Operational Amplifiers and Programmable Gain Amplifiers (OP)

• Three independent Rail-to-Rail configurable gain amplifiers: OP0/OP1/OP2

• OP1/OP2 can be set to comparator (CMP) mode
  -- Output can be used as EPWM fault trigger source
  -- Hysteresis voltage fixed at 10~15mV in CMP mode
  -- Response time in CMP mode: typical 50ns

• All three OPs can be configured as PGA
  -- Non-inverting gains: 4/8/16/32
  -- Inverting gains: 3/7/15/31

• Each OP has independent external pins for non-inverting input, inverting input, and output

• Outputs of the three OPs are respectively shared with three ADC channels, results readable via ADC result registers

• OP1/OP2 outputs can be routed to positive inputs of CMP0 and CMP3

• Input offset voltage ≤10mV, requires zero calibration

• Slew rate ≥10V/µs

Three Analog Comparators CMP0/1/2

• Outputs of the three CMPs can be connected to PCAP module

• Each CMP has an independent external positive input pin

• Positive input of CMP0 (CMP0P) can also be switched to OP1 or OP2 output

• Negative inputs of the three CMPs can be independently switched to:
  -- Common external negative input pin CMPxN shared by the three CMPs
  -- Built-in DAC output
  -- Built-in virtual neutral point

• CMP0/1/2 interrupts can wake up STOP Mode

• Hysteresis voltage four options: 0/5/10/20mV

• Response time: typical 50ns

One Independent Analog Comparator CMP3

• Positive input of CMP3 can be switched to:
  -- External input pin CMP3P
  -- OP1 or OP2 output

• Negative input of CMP3 can be switched to:
  -- External input pin CMP3N
  -- Built-in DAC output
  -- 16-step divided output from VREF

• Interrupt can wake up STOP Mode

• Hysteresis voltage four options: 0/5/10/20mV

• Response time: typical 50ns

Temperature Sensor

• Temperature sensor voltage can be measured via ADC circuit
  -- Using 2.4V internal reference voltage as reference
  -- ADC conversion value increases by a fixed amount per 1°C rise

Math Rhythm Unit (MR)

• Provides input/output interface

• Includes multiple operation acceleration modules: division, square root, trigonometric functions, arctangent, SVPWM, coordinate transformation, PID, etc.

• Data transferred via DMA

Resource Block Diagram

Acroview's AP8000 universal programmer has become a benchmark professional programming solution in the industry. This device supports flexible configurable one-to-one and one-to-eight programming modes, and provides online and offline operation modes. Dedicated programming solutions have been developed for memory chips such as eMMC and UFS. It can comprehensively cover offline (bare chip) and on-board programming needs for all series of SinOne microelectronics. The AP8000 adopts an innovative modular design of three core modules: main unit, baseboard, and adapter, giving the device excellent compatibility and expandability. As a universal programming platform, it not only adapts to various programmable chips on the market but also, with its stable and efficient performance, serves as a core component of Acroview's automated batch programming system IPS5800S, efficiently handling large-scale chip programming tasks to meet mass production requirements.

The AP8000 main unit features flexible connectivity, equipped with both USB and NET interfaces, enabling convenient networking of multiple programmers. Through networking, users can easily achieve synchronized control of multiple programmers and efficiently carry out parallel programming operations. In terms of safety, the main unit has built-in intelligent safety protection circuits that monitor chip placement status and circuit connections in real time. If abnormalities such as reverse insertion or short circuit are detected, it immediately triggers a power-off protection mechanism, fully safeguarding the safe operation of chips and the programmer. The main unit houses a high-speed FPGA chip, greatly enhancing data transmission and processing efficiency, ensuring a smooth and efficient programming process. To enhance ease of use, an SD card slot is provided on the back of the main unit. Users can save project files generated on a PC to an SD card, insert it into the slot, and then use the physical buttons on the programmer to select, load, and execute programming, enabling standalone operation without a PC. This design not only reduces dependence on computer hardware configuration but also simplifies the workspace setup, significantly improving operational flexibility.

In terms of expandability and compatibility, the AP8000 uses a modular combination of baseboard and adapter board, effectively expanding the main unit's functional boundaries. Currently, the device supports products from all major semiconductor manufacturers, covering well-known brands such as SK hynix, Micron, SANDISK, ASR, Kingston, etc. Its supported device types are extensive, including NAND, NOR, MCU, CPLD, FPGA, EMMC, etc., and it is fully compatible with various industry-standard file formats such as Intel Hex, Motorola S, Binary, POF, providing users with a one-stop, full-scenario chip programming solution.

Company Introduction

About SinOne Microelectronics: SinOne Microelectronics (SinOne) was founded in 2011. It is an integrated circuit supplier that provides innovative and competitive MCU platforms for electronic product developers based on market demands. The company leverages core technology, advanced design capabilities, and digital-analog integration expertise to offer high-anti-interference and high-reliability 8-bit and 32-bit microcontroller (MCU) products. All company products have independent intellectual property and are in a leading technical position.

About Acroview: Acroview is a national-level "Little Giant" enterprise specializing in the R&D, production, and sales of semiconductor chip testing and programming equipment. The company is committed to empowering the entire industry chain, including Fabless, IDM, OSAT, wafer fabs, and end-device companies, through innovative semiconductor testing technologies and solutions. Acroview's pioneering Auto Burn-In (ABI) system greatly improves customer chip burn-in testing efficiency and reduces per-DUT testing costs. Additionally, the company provides equipment products and solutions for various stages including PSV, CP, FT, ABI, SLT, and programming. Acroview seamlessly integrates its leading product technology, system-level expertise, and globally distributed R&D and sales service networks to create value for customers to achieve leadership in market competition.